The invention relates to a semiconductor device comprising a semiconductor body which is provided at a surface with a non-volatile memory of a type in which each memory cell comprises an insulated-gate field-effect transistor, whose threshold voltage, which depends upon the stored information, is determined by electrical charge that can be stored in a charge storage region which is defined in an insulating layer covering the channel region. This transistor further includes a gate electrode capacitively coupled to the charge storage region and source and drain zones of a first conductivity type which are separated by a pn junction from a layer-shaped part of the semiconductor body of the second conductivity type surrounding the zones, means being provided for applying a given voltage, for example a supply voltage, to the layer-shaped part of the semiconductor body during operation, and means being provided for applying between the gate electrode and a conductive region adjoining the oxide layer, during erasing and/or writing (for example, a part of the semiconductor body located under the charge storage region and hereinafter designated the substrate region), a voltage difference such that an electrical field is produced across the insulating layer whereby charge flow can occur between the charge storage region and the conductive region/substrate region.
Memories of the kind mentioned here, generally designated as EEPROMs or E.sup.2 PROMs and EPROMs, are programmable memories which can be erased electrically or by means of (UV) radiation and can then be electrically reprogrammed. In a frequently-used construction, the charge storage region is constituted by a floating gate electrode which is embedded in the insulating layer above the channel region. The said gate electrode may be formed on the insulating layer or may be located in the semiconductor body in the form of a diffused zone. The conductive region is mostly constituted by a region in the substrate. In particular embodiments, the conductive region may also be constituted by a conductive layer which is located above the floating gate.
The cell may be written into (programmed) and erased by quantum tunelling of electrons through the insulating layer. Such a semiconductor device is described inter alia in U.S. Pat. No. 4,377,857. In another embodiment, in which the charge storage region consists of a floating gate electrode, the operation of programming/erasing is effected by injection of hot charge carriers which are generated in the semiconductor body by avalanche breakdown. In a further embodiment, the charge storage region can be constituted by the interface layer between two different dielectrics, such as silicon dioxide and silicon nitride. Such memories are often designated as MNOS memories.
In embodiments having a floating gate, the layer-shaped part of the semiconductor body mentioned above can cover the whole semiconductor substrate, which in this case, apart from the zones formed in it, can be mainly of the second conductivity type. In the case of an MNOS memory, the layer-shaped part of the semiconductor body can comprise a pocket (or well) formed in a semiconductor substrate of the one conductivity type by means of so-called C-MOS technology.
For the sake of simplicity, the following description will relate to memories having a floating gate, in which the operation of writing/erasing is effected by tunnelling. However, it should then be noted that, because problems similar to those described for this type of EEPROM may also arise for other types of EEPROMS and EPROMS, the invention can also be used in these other types.
In memories based on the quantum tunnelling mechanism, the oxide above the drain zone has been locally made very thin, for example a few tens of Angstrom units. A high voltage can be applied to the gate electrode, whereas a low voltage, especially substrate voltage or ground potential, is applied to the drain. Between the floating gate (which is capacitively strongly coupled to the gate electrode) and the drain zone (which constitutes the substrate region mentioned in the opening paragraph) there is produced such a strong electrical field that (in the case of an n-channel MOST) it is possible for electrons to tunnel from the drain region via the thin oxide to the floating gate. By inversion of the field, a tunnel current in the opposite direction can be obtained. Thus, it is possible to write and erase a cell.
The gate electrodes, which are interconnected by word or data lines, extend not only above the channel regions, but also above the field oxide between the memory cells and can form a parasitic field effect transistor, in which the field oxide is the gate dielectric and the said drain of the memory transistor is the source. When the threshold voltage is lower than the said high voltage which during writing or erasing is applied to the gate electrode, this transistor becomes conducting. This problem could be solved by the use of a process in which high voltages are permissible without parasitic thresholds being exceeded. However, nowadays it is often desirable to integrate EEPROMs together with VLSI circuits, such as, for example, in microprocessors, because this allows the user to adapt the systems in a simple manner. The usual VLSI processes are optimized for applications which use low voltages (smaller than 10 V). As a result, problems can arise when programming the (E)EPROMs, which require a higher voltage, for example about 20 V. In general, a small current is required for programming the floating gates by means of tunnelling. Therefore, the high programming voltage can be generated internally by a charge pump, which in general can supply only a limited current. When the threshold voltages of the parasitic transistors are exceeded, as a result of which these transistors become conducting, as described above, leakage paths can be formed in the circuit, which limit the maximum voltage supplied by the pump. Additionally, other disadvantages due to parasitic transistors may occur.
This leakage path could be eliminated by replacing the material of the gate electrode at the critical areas (mostly polycrystalline silicon or poly) by another material, for example, a metal. Further, the threshold voltage of the parasitic MOS transistors may be increased by increasing the doping concentration under the field oxide. A further solution could consist of providing a conductive screening layer under the gate electrode connections, to which a low voltage can be applied. These solutions can be used for the peripheral electronics but are not practical for the storage matrix itself because they occupy an excessively large amount of space.